AMD Launches the Xiaolong Embedded 9006 Series SP7 Processors, with Up to 1.8 Times Increased Throughput
The Block
57m ago
Ai Focus
AMD releases the Xiaolong embedded 9006 series processors based on the Zen 6-core architecture, with up to 256 cores and 512 threads. They are the first to support PCIe Gen6 and CXL 3.1, and are designed for embedded applications such as semiconductor ATE testing, enterprise storage, and high-end network firewalls.
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News from the IT family on November 11th: AMD has released today (November 11th) the Xiaolong (EPYC) embedded 9006 series SP7 processors, based on the Zen 6-core architecture, with up to 256 cores and 512 threads. These processors are the first to be implemented on embedded platforms supporting PCIe Gen6 and CXL 3.1, paired with 16-channel DDR5 / MRDIMM memory. The product's lifecycle is 7 years.

Different from the AMD HiLong 9006 series servers released in September CPU (targeting agents AI, cloud computing, enterprise applications, etc.), the newly released embedded 9006 series SP7 processors are mainly aimed at key embedded scenarios such as semiconductor ATE testing equipment, enterprise storage, and high-end network firewalls.

In terms of slot specifications, the AMD Xuelong Embedded 9006 series adopts the new generation of SP7 specifications, while the previous 9005 series used SP5 slot specifications; the two are not physically compatible. The SP7 is a high-performance, high-density server platform within the EPYC 9006 series, utilizing LGA 7536 slots and supporting 1P/2P (single or dual paths) servers.

In terms of specifications, the AMD Xielong Embedded 9006 series has been upgraded to support PCIe Gen6 (96 channels @64GT/s) and CXL 3.1. In terms of memory, it supports 16 channels with a speed of MRDIMM 12800MT/s, which is 2.7 times higher than the previous generation's memory bandwidth.

IT Note: The 2.7 times mentioned here is based on the fact that the EPYC Embedded platform (with SP7 at 9756 and Zen at 6) supports a theoretical peak bandwidth of 12800 MT/s per slot, with a single-slot theoretical peak bandwidth of 1638 GB/s; whereas the previous generation EPYC (with SP5 at 9005 and Zen at 5, DDR5-6400 at MT at /s) had a theoretical peak bandwidth of 614 GB/s per slot.

The multi-core throughput of this series has increased by up to 1.8 times compared to its previous generation, the firewall throughput has increased by 1.3 times, and the storage acceleration ISA-L performance has increased by 1.5 times. At the same time, it integrates ART trusted roots and Caliptra open-source trust modules, supports post-quantum firmware encryption, and provides comprehensive security protection from startup to runtime, meeting the long-term supply needs of the industrial sector.

Product SKU covers 64-256 cores; the 128-core model will be shipped on November 15th. The rest of the models SKU will be delivered gradually by the end of the year. Manufacturers such as Samsung, Lihua, Portwell, and IEI have already developed hardware products based on this platform.

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